| AES_H8 Project Status | |||
| Project File: | aes_h8.ise | Current State: | Programming File Generated |
| Module Name: | aes_h8 |
|
No Errors |
| Target Device: | xc2s200-5pq208 |
|
111 Warnings |
| Product Version: | ISE 9.1i |
|
? 3 18 04:03:47 2007 |
| AES_H8 Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 1,229 | 4,704 | 26% | |
| Number of 4 input LUTs | 3,231 | 4,704 | 68% | |
| Logic Distribution | ||||
| Number of occupied Slices | 1,900 | 2,352 | 80% | |
| Number of Slices containing only related logic | 1,900 | 1,900 | 100% | |
| Number of Slices containing unrelated logic | 0 | 1,900 | 0% | |
| Total Number of 4 input LUTs | 3,234 | 4,704 | 68% | |
| Number used as logic | 3,231 | |||
| Number used as a route-thru | 3 | |||
| Number of bonded IOBs | 20 | 140 | 14% | |
| IOB Flip Flops | 8 | |||
| Number of GCLKs | 1 | 4 | 25% | |
| Number of GCLKIOBs | 1 | 4 | 25% | |
| Total equivalent gate count for design | 29,786 | |||
| Additional JTAG gate count for IOBs | 1,008 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | ? 3 18 03:59:20 2007 | 0 | 109 Warnings | 2 Infos |
| Translation Report | Current | ? 3 18 04:00:11 2007 | 0 | 0 | 0 |
| Map Report | Current | ? 3 18 04:00:29 2007 | 0 | 2 Warnings | 2 Infos |
| Place and Route Report | Current | ? 3 18 04:02:52 2007 | 0 | 0 | 2 Infos |
| Static Timing Report | Current | ? 3 18 04:03:02 2007 | 0 | 0 | 3 Infos |
| Bitgen Report | Current | ? 3 18 04:03:46 2007 | 0 | 0 | 0 |